一種新的故障測(cè)試率的概率估計(jì)方法

丁瑾; 胡健棟

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一種新的故障測(cè)試率的概率估計(jì)方法

丁瑾, 胡健棟

文章導(dǎo)航 > 電子與信息學(xué)報(bào) > 1995 > 17(1): 55-59

丁瑾, 胡健棟. 一種新的故障測(cè)試率的概率估計(jì)方法[J]. 電子與信息學(xué)報(bào), 1995, 17(1): 55-59.

引用本文:

丁瑾, 胡健棟. 一種新的故障測(cè)試率的概率估計(jì)方法[J]. 電子與信息學(xué)報(bào), 1995, 17(1): 55-59.

Ding Jin, Hu Jiandong. A NEW PROBABILISTIC APPROACH TO ESTIMATE TESTABILITY[J]. Journal of Electronics & Information Technology, 1995, 17(1): 55-59.

Citation:

Ding Jin, Hu Jiandong. A NEW PROBABILISTIC APPROACH TO ESTIMATE TESTABILITY[J]. Journal of Electronics & Information Technology, 1995, 17(1): 55-59.

丁瑾, 胡健棟. 一種新的故障測(cè)試率的概率估計(jì)方法[J]. 電子與信息學(xué)報(bào), 1995, 17(1): 55-59.

引用本文:

丁瑾, 胡健棟. 一種新的故障測(cè)試率的概率估計(jì)方法[J]. 電子與信息學(xué)報(bào), 1995, 17(1): 55-59.

Ding Jin, Hu Jiandong. A NEW PROBABILISTIC APPROACH TO ESTIMATE TESTABILITY[J]. Journal of Electronics & Information Technology, 1995, 17(1): 55-59.

Citation:

Ding Jin, Hu Jiandong. A NEW PROBABILISTIC APPROACH TO ESTIMATE TESTABILITY[J]. Journal of Electronics & Information Technology, 1995, 17(1): 55-59.

一種新的故障測(cè)試率的概率估計(jì)方法

丁瑾,
胡健棟

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出版歷程
- 收稿日期: 1993-09-28
- 修回日期: 1994-05-03
- 刊出日期: 1995-01-19

A NEW PROBABILISTIC APPROACH TO ESTIMATE TESTABILITY

摘要

摘要: 本文提出了一種新的估計(jì)故障測(cè)試率的方法。它使用了無故障模擬的概念,觀察率和控制率被定義成觀察和控制電路節(jié)點(diǎn)的概率;分析了電路中節(jié)點(diǎn)的隨機(jī)信號(hào)的概率分布;證明了控制率是服從正態(tài)分布的;依此獲得了故障測(cè)試率的無偏估計(jì)。按照觀察率的定義,我們處理了扇出節(jié)點(diǎn)。對(duì)一些實(shí)際的電路,利用此法所獲得的故障覆蓋與故障模擬結(jié)果非常吻合。
- 概率估計(jì)方法; 控制率; 觀察率; 故障測(cè)試率; 故障覆蓋
Abstract: A new approach to calculate fault detection probabilities is presented. The fault-free simulation is used in this approach. The quantities of controllabilities and observabilities are defined as probabilities of controlling and observing the nodes in the circuit. The probability distribution of random signals at circuit nodes is analyzed, and it is proved that controllability is in normal distribution. Thus the unbiasing estimate of fault detection probability can be obtained. According to the concept of observability, the fanout nodes are dealt with. For actual circuits the fault coverage obtained from this approach agrees favorably with the fault simulation results.

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參考文獻(xiàn)(1)

Lala P K. Fault tolerant and testable hardware design. London: Prentice-Hall International Inc., 1985, Chapter 6, Section 1.[2]Agrawal V D. Journal of Digital Systems, 1981, 5(3):189-202.[3]Franc Brgler, On testability analysis of combinational networks. Proc. of IEEE International Symposium on Circuits and Systems. Montreal: 1984, 221-225.[4]Agrawal V D, Seth S C. Probabilistic testability. Proc. of IEEE International Conference on Computer Design. New York: 1985, 562-565.[5]Hans-Joachim Wunderlich, PROTEST: A tool for probabilistic testability analysis, Proc. of 22nd Design Autumation Conference- New York: 1985, 204-211.[6]Agrawal S J, Agrawal V D. IEEE Design and Test of Computers, 1985, 2(1):38-44.[7]潘榆奇,等.一個(gè)實(shí)用化的測(cè)試產(chǎn)生系統(tǒng)--COMPA ATPGS.北京:中國(guó)科學(xué)院計(jì)算技術(shù)研究所CAD開放研究實(shí)驗(yàn)室年報(bào),1991,334-342.[8]Feller W. An introduction to probability theory and its applications, Vol. 1, New York: Wiley, 1957, Chapter 7, Section 2.[9]Dacunha-Castelle Didier. Probability and statistics. New York: Springer-Verlag, 1986, Chapter 5, Section 3 and Chapter 1, Section 3.[10]Papoulis A. Probability, random variables and stochastic processes. New York: McGraw Hill, 1984, Ch. 2, 6.[11]韓崇昭，等.隨機(jī)系統(tǒng)理論.西安:西安交通大學(xué)出版社,1986,第三章,第二節(jié).[12]劉志萬(wàn).實(shí)驗(yàn)數(shù)據(jù)的統(tǒng)計(jì)分析和計(jì)算機(jī)處理.合肥:中國(guó)科學(xué)技術(shù)大學(xué)出版社,1989,第二章,第一節(jié).

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